Characteristics of a CISC design

Characteristics of a CISC design


While the chips that emerged from the 1970s and 1980s followed their own unique design paths, most were bound by what we are calling the "CISC Design Decisions". These chips all have similar instruction sets, and similar hardware architectures.

In general terms, the instruction sets are designed for the convenience of the assembly-language programmer and the hardware designs are fairly complex.

Instruction sets

The design constraints that led to the development of CISC (small amounts of slow memory, and the fact that most early machines were programmed in assembly language) give CISC instruction sets some common characteristics:

Hardware architectures

Most CISC hardware architectures have several characteristics in common:

The ideal CISC machine

CISC processors were designed to execute each instruction completely before beginning the next instruction. Even so, most processors break the execution of an instruction into several definite stages; as soon as one stage is finished, the processor passes the result to the next stage:

In an ideal CISC machine, each complete instruction would require only one clock cycle (which means that each stage would complete in a fraction of a cycle.) In fact, this is the maximum possible speed for a machine that executes 1 instruction at a time.


A realistic CISC machine

In reality, some instructions may require more than one clock per stage, as the animation shows. However, a CISC design can tolerate this slowdown since the idea behind CISC is to keep the total number of cycles small by having complicated things happen within each cycle.


CISC and the Classic Performance Equation

The usual equation for determining performance is the sum for all instructions of (the number of cycles per instruction * instruction cycle time) = execution time.

This allows you to speed up a processor in 3 different ways --- use fewer instructions for a given task, reduce the number of cycles for some instructions, or speed up the clock (decrease the cycle time.)

CISC tries to reduce the number of instructions for a program, and (as we will see) RISC tries to reduce the cycles per instruction.