Characteristics of a CISC design
While the chips that emerged from the 1970s and 1980s followed their own unique design paths, most were bound by what we are calling the "CISC Design Decisions". These chips all have similar instruction sets, and similar hardware architectures.
In general terms, the instruction sets are designed for the convenience of the assembly-language programmer and the hardware designs are fairly complex.
The design constraints that led to the development of CISC (small amounts of slow memory, and the fact that most early machines were programmed in assembly language) give CISC instruction sets some common characteristics:
- A 2-operand format, where instructions have a source and a destination. For example, the add instruction "add #5, D0" would add the number 5 to the contents of register D0 and place the result in register D0.
- Register to register, register to memory, and memory to register commands.
- Multiple addressing modes for memory, including specialized modes for indexing through arrays
- Variable length instructions where the length often varies according to the addressing mode
- Instructions which require multiple clock cycles to execute. If an instruction requires additional information before it can run (for example, if the processor needs to read in two memory locations before operating on them), collecting the extra information will require extra clock cycles. As a result, some CISC instructions will take longer than others to execute.
Most CISC hardware architectures have several characteristics in common:
- Complex instruction-decoding logic, driven by the need for a single instruction to support multiple addressing modes.
- A small number of general purpose registers. This is the direct result of having instructions which can operate directly on memory and the limited amount of chip space not dedicated to instruction decoding, execution, and microcode storage.
- Several special purpose registers. Many CISC designs set aside special registers for the stack pointer, interrupt handling, and so on. This can simplify the hardware design somewhat, at the expense of making the instruction set more complex.
- A "Condition code" register which is set as a side-effect of most instructions. This register reflects whether the result of the last operation is less than, equal to, or greater than zero, and records if certain error conditions occur.
CISC processors were designed to execute each instruction completely before beginning the next instruction. Even so, most processors break the execution of an instruction into several definite stages; as soon as one stage is finished, the processor passes the result to the next stage:
In an ideal CISC machine, each complete instruction would require only one clock cycle (which means that each stage would complete in a fraction of a cycle.) In fact, this is the maximum possible speed for a machine that executes 1 instruction at a time.
- An instruction is fetched from main memory.
- The instruction is decoded: the controlling code from the microprogram identifies the type of operation to be performed, where to find the data on which to perform the operation, and where to put the result. If necessary, the processor reads in additional information from memory.
- The instruction is executed. the controlling code from the microprogram determines the circuitry/hardware that will perform the operation.
- The results are written to memory.
In reality, some instructions may require more than one clock per stage, as the animation shows. However, a CISC design can tolerate this slowdown since the idea behind CISC is to keep the total number of cycles small by having complicated things happen within each cycle.
The usual equation for determining performance is the sum for all instructions of (the number of cycles per instruction * instruction cycle time) = execution time.
This allows you to speed up a processor in 3 different ways --- use fewer instructions for a given task, reduce the number of cycles for some instructions, or speed up the clock (decrease the cycle time.)
CISC tries to reduce the number of instructions for a program, and (as we will see) RISC tries to reduce the cycles per instruction.