Hardware Systems
© Copyright Brian Brown, 1992-2000. All rights reserved.

Part 2: Buses and Interfaces

1: An Introduction to Bus Systems
This section is all about bus systems in computers, specifically the bus systems used in IBM-PC and compatibles. A bus system is a highway that interconnects two or more devices. The highway consists of a number of wires that perform the following functions.

• data transfer
• timing and synchronisation of data
• bus arbitration

In a designated transfer, one device is the master, and the other device(s) are slaves. The master device controls the transfer of data and issues commands to accomplish this.

A multi-master bus supports more than one master on the bus at a time. This is essential for high performance workstations and file-servers.

1.1 ISA (Industry Standard Architecture)
Originally developed for the IBM-PC computer (8086, 8 bit bus), it was extended in 1984 to support 16 bits when the 80286 AT computer was introduced. Its main features are

• single bus master
• support for up to 16MB of memory
• 8/16 bit data width
• interrupts cannot be shared by more than card
• widely accepted and many cards available
• 8MHz clock rate for data transfers

With the development of the 80386 processor, many manufacturers did not upgrade the bus to accommodate the larger address and data paths. This was done on the basis that the majority of plug-in cards were all 16bit ISA.

A bus controller chip provides the interface between the processor, memory sub system and the peripheral devices. Whilst the processor can talk to the memory sub system at 33MHz, it is forced to talk to the peripheral devices at 8MHz due to the ISA bus controller chip.

The advent of 32 bit operating systems like OS/2 and Windows NT pushed the ISA bus into overload, where the major problem became the volume of data being moved around the computer system. The ISA bus is not fast enough to handle these large amounts of data, and thus slows the system down (is a bottleneck).

Another problem with the ISA bus is the one interrupt, one card syndrome. The ISA bus uses edge level interrupts. An interrupt is a request from a peripheral device (like a disk controller or video card) for service by the processor. An edge level interrupt is an interrupt that is signaled by the peripheral device changing the Voltage State (from 0 to 1 or 1 to 0).

The ISA bus supports 14 interrupts on the bus (IRQ2 to IRQ15). An edge interrupt can only be used by a single peripheral card (ie, cannot be shared).

The ISA connector looks like

The following table lists the interrupts and their normal card usage for the PC.

1.2 EISA (Extended Industry Standard Architecture)
This is a 32-bit bus extension to ISA, designed for the 386 and 486 processors. The main features are,

• full compatibility with ISA (supports cards)
• 32 bit data transfer path
• high data transfer rates (33MB/s)
• multiple bus master support
• shared interrupt support
• memory addressing up to 4GB
• automatic card configuration
• cards are expensive

The connectors allow both ISA and EISA boards to be used. The bus design was announced on September 13th, 1988, and is supported by most manufacturers of high end PC's. Today, in 1999, EISA is nearly obsolete and has been replaced by PCI (Peripheral Connect Interface).

The EISA bus is downward compatible with ISA cards. They simply plug in and function normally. EISA supports a much higher data transfer rate on EISA cards, by providing a larger data path (8/16/32 bits wide) and a higher bus rate of 10MHz. The 16MB memory limit of the ISA bus is overcome in EISA by using 32 address lines, giving access to 4GB of memory. Interrupts may be either level or edge sensitive. When EISA cards are configured to use level interrupts, then several cards may share the same interrupt line.

A major problem of the ISA bus is the use of DIP switches and jumpers to configure boards. Often, two or more boards are configured with the same parameters (interrupt number or port address), which causes a hardware conflict and prevents the computer from working reliably. A handy feature of EISA boards is self-configuration. There are no DIP switches or jumpers to configure. The board automatically configures itself to use a configuration not in use by another board.

An EISA connector looks like

1.3 Peripheral Connect Interface Bus
PCI has been developed by Intel Corporation and has the support of some major computer manufacturers (IBM, NEC, and Compaq). PCI-bus supports 10 peripherals per bus, and supports bus mastering. It is slightly slower than VL-bus, but three times faster than either EISA or MCA. It is ideally suited for high-speed data transfers in graphic situations. PCI-bus runs at 33MHz, yielding a maximum data transfer rate of 132Mbytes per second.

New specifications have been developed to support 64 bit bus systems and 3.3volt systems. The cards are keyed, so that 5V and 3.3V boards plug into their respective connectors (there is a different connector for each voltage type). By using a buffered design, PCI allows multiple devices to be connected, because the buffers provide isolation and amplification of the signals.

PCI will support the automatic configuration of devices, in that registers within the PCI chipset will keep an inventory of available resources (like interrupts) and will allocate a free resource to a new PCI card when inserted. PCI uses burst reads and writes for all bus transfers, whether its memory or I/O, and each burst transfer have an indefinite length. The burst transfer continues till the master or target device requests the transfer to end. Each PCI device is equipped with a latency timer, which is used to define the maximum amount of time the device is allowed to use the bus.

1.4 A Comparison of Bus Types

Courtesy www.intel.com for a 486DX2-66MHz identically configured PC.

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© Copyright Brian Brown, 1992-2000. All rights reserved.